Embodiments of the present disclosure relate to a data output circuit and a memory device including the same, and more particularly, to a data output circuit for multiplexing a plurality of pieces of data and outputting an output data signal and a memory device including the data output circuit.
A memory device may include an output driver for outputting an internal signal to outside. An output driver typically includes a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor, which are connected between a power line and a ground line. Generally, synchronous dynamic random access memory (hereinafter, referred to as SDRAM) may operate by using a single data rate (SDR) method wherein data is synchronized with a rising edge of a system clock, and thus, a piece of data is input/output in a period of a clock. However, as a frequency of a system clock increases, there is typically a demand for an increase in a speed of data input/output. Accordingly, a double data rate (DDR) method has been developed wherein two pieces of data are input/output in a period of a clock by respectively inputting/outputting a piece of data with respect to a rising edge and a falling edge of a system clock. High-speed data transmission may be performed by using the DDR method even if an internal operation frequency is not increased. Additionally, recently, a low-power DDR (LPDDR) method has been employed. The LPDDR method may enable high-speed data transmission with low power consumption.
At present, according to a structure used in the LPDDR method, a plurality of data signals, which are transmitted at a frequency less than a clock frequency, are multiplexed, and thus, output to an output pad via ends of several output drivers. Multiplexed data may be transmitted to the output pad at a frequency identical to the clock frequency. However, since a data output unit using this structure in the LPDDR method includes a multiplexer implemented as a plurality of transistors for performing a multiplexing operation, it may be difficult to accurately transceive an output data signal at high speed due to a parasitic effect of the plurality of transistors and an increase in an equivalent resistance of the plurality of transistors.